The present invention relates generally to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device which reduces interference between adjoining gates and a method for manufacturing the same.
As the design rule of a semiconductor device decreases, limitations are encountered when attempting to attain a target threshold voltage using a conventional planar channel structure. As a result of the limitations, research has been directed towards a semiconductor device having three-dimensional recessed channels.
A semiconductor device having recessed channels is realized by recessing the channel forming areas of a semiconductor substrate and then forming gates in and over the recessed channel areas. A semiconductor device having recessed channels has advantages over a conventional semiconductor device having planar channels, including the advantage of an increased effective channel length allowing a required threshold voltage to be obtained.
In order to raise the integration level of a DRAM (dynamic random access memory), it is essential to decrease the size of a cell transistor. However, as the size of the cell transistor is decreased to raise the integration level, a problem arises in that the data stored in a cell is likely to be lost when interference is caused by the operation of a transistor in an adjoining cell. In an effort to remove the interference caused by the adjoining gate, a method of depositing a highly doped polysilicon layer around an active region and a local damascene method of keeping a field oxide region (on which a gate poly is to be deposited) from being etched have been disclosed in the art.
Conventional methods for removing the interference caused by an adjoining gate require that an additional bias voltage be supplied and also require additional processes, which in turn deteriorate the effectiveness of the conventional methods.